As known in the art, through-substrate vias (referred to herein as TSVs), which are commonly referred to as through-silicon vias, are vertical electrical connections that extend from one of the electrically conductive levels formed on the top surface of the IC die (e.g., one of the metal interconnect levels) to the backside (bottom) surface of the IC die. TSVs are used as power TSVs (e.g., for VDD, VSS or ground) and/or signal TSVs. Signal TSVs are generally formed close to active circuitry, such as within 5 to 20 μm from the active circuitry. The TSV planar (x-y) dimensions can be about 5 to 50 μm, with aspect ratios (ARs) from about 5:1 to 20:1.
TSVs allow the TSV comprising IC to be bonded on both sides and utilize vertical electrical paths to couple to other IC devices (e.g., on a die, wafer) or to mount to a package substrate positioned below the IC die. The vertical electrical paths are significantly shortened relative to conventional wire bonding technology, generally leading to significantly faster device operation of the IC.
TSVs can be formed in a “via-first,” a “via-middle,” or a “via-last” approach. In the via-first approach the TSVs are formed in the wafer fab during front end processing. Via-first can comprise TSV formation before transistors are formed. Via-middle can take place after transistor formation, such as formed between the contact level and first metal, or after one or more levels of metal interconnect, but before passivation. In contrast, the via-last approach takes place in assembly and packaging and typically forms the TSVs from the bottom surface of the IC die after wafer processing is completed (i.e. after passivation processing).
In a typical via-first process, vias are formed to a depth (e.g., 10 to 300 μm) that is less than the full wafer thickness (e.g., 400 μm to about 775 μm for 12 inch wafers) using chemical etching, laser drilling, or one of several energetic methods, such as Reactive Ion Etching (RIE). Once the vias are formed, they are generally framed with a dielectric liner to provide electrical isolation from the surrounding semiconductor substrate. The dielectric liner is generally formed from silicon oxide, silicon nitride, or silicon oxynitride.
The vias are then made electrically conductive by filling the vias with an electrically conductive filler material (e.g., copper, tungsten or doped polysilicon) to form embedded TSVs. The bottom of the embedded TSV is generally referred to as an embedded TSV tip. In the case the electrically conductive filler materials comprises a metal, some metals (e.g., copper) are known to provide band gap states near the center of the semiconductor's band gap. As a result, such metals if highly mobile in the semiconductor can significantly degrade minority carrier lifetimes in the semiconductor, and cause problems such as significantly increased junction leakage or shift in transistor threshold voltage.
To prevent escape of the metal into the surrounding semiconductor, a diffusion barrier layer is generally deposited on the dielectric liner. The diffusion barrier layer generally comprises refractory-metal comprising materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or ruthenium (Ru). Such diffusion barrier layer layers are known to be effective against diffusion of most metals, including copper. Diffusion barrier layer films can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD) also known as sputtering, evaporative deposition, or pulsed laser deposition. PVD processes are generally preferred due to lower cost as compared to CVD processes.
For via-first and via-middle processes, a backgrinding step is conventionally used to thin the wafer by removing a sufficient thickness of the substrate (e.g., 300 to 500 μm) from the bottom surface of the wafer to reach the embedded TSV tip to expose the electrically conductive filler material at the distal end of the TSV tip.
In a via-last process backgrinding generally takes place before via formation, and the TSVs are formed beginning at the bottom of the wafer. However, analogous to via-first processing, via-last processing generally includes a dielectric liner to provide electrical isolation to the surrounding semiconductor substrate, followed by filling the lined via with an electrically conductive filler material (e.g., copper), and a diffusion barrier layer between the TSV filler material and the dielectric liner when the TSV filler material comprises a fast diffusing and minority lifetime killing metal (e.g., copper).